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AMD Next Generation Quad Core Processor Power Saving Feature

by Shivaranjan on August 26, 2006


Recently AMD revealed that it had completed the design phase of its native quad core processors. I came across some AMD slides in which I came to know about how their new quad core processors save power. The native quad core processors will feature the following:

  • Will feature dynamic independent core engagement (DICE), power saving feature
  • 32B Instruction fetch
  • Improved branch prediction
  • Out of order load execution
  • Upto 4 DP Flops/cycle
  • Dual 128 bit SSE data flow
  • Dual 128 bit loads per cycle
  • Bit manipulation extensions
  • Four x16 Hypertransport Link (max of 5.2 GT/s)
  • Enhanced crossbar
  • Enhanced power management and RAS
  • Shared L3 cache, Independent L1 and L2 cache for each core.
  • will be manufactured using 65nm technology

These new processors save power by dynamically and individually adjusting the core frequencies. This means that if enough load is not given to the processor it will halt cores which donot have load. According to the slides the AMD quad core will become dual core when there is not enough load on the system. :D But at what point the power management system decides to temporarily shut down one core or more isn’t made clear. Refer to the slides below which illustrates this new power saving feature.
These features look really very promising and I feel that AMD has started to do its homework to regain its lost crown.

Here are the slides of AMD Quad Core Processor:

Click on the images to enlarge

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